By Yongquan Fan

ISBN-10: 9048193974

ISBN-13: 9789048193974

High-Speed Serial Interface (HSSI) units became frequent in communications, from the embedded to high-performance computing platforms, and from on-chip to a large haul. checking out of HSSIs has been a demanding subject due to sign integrity concerns, lengthy attempt time and the necessity of pricey tools. Accelerating attempt, Validation and Debug of excessive pace Serial Interfaces offers leading edge try and debug techniques and precise directions on easy methods to arrive to useful try of recent high-speed interfaces.

Accelerating try out, Validation and Debug of excessive pace Serial Interfaces first proposes a brand new set of rules that allows us to accomplish receiver attempt greater than one thousand instances quicker. Then an under-sampling dependent transmitter attempt scheme is gifted. The scheme can correctly extract the transmitter jitter and end the full transmitter try inside of 100ms, whereas the attempt often takes seconds. The publication additionally provides and exterior loopback-based checking out scheme, the place and FPGA-based BER tester and a singular jitter injection approach are proposed. those schemes may be utilized to validate, try and debug HSSIs with info expense as much as 12.5Gbps at a reduce attempt rate than natural ATE strategies. moreover, the ebook introduces an efficieng scheme to enforce excessive functionality Gaussian noise turbines, appropriate for comparing BER functionality lower than noise conditions.

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Extra resources for Accelerating Test, Validation and Debug of High Speed Serial Interfaces

Example text

The final result is that there is a control system that adjust the VCO to track the input clock rate – it obviously has to be designed to perform such function in a stable and predictable way. Variable Delay Input Serial Data D Retimed Data Q Recovered Clock Edge Detector PLL φnoise(f) φin(f) PFD LF VCO φout(f) 1/N Fig. 3-2. Block diagram of the CDR with a typical linear PLL To illustrate the characteristics of the PLL, we use φin(f) to denote the PLL input phase of the signal and φout(f) to denote the PLL output phase in Figure 3-2.

The input signal to the PLL comes from the Edge Detector, which recovers the clock-like waveform from the signal degraded due to a multitude of effects at higher rates. The Phase Frequency Detector (PFD) compares the frequency and phase difference between the edge detector output and the recovered clock signal, and produces narrow control pulses with widths proportional to the phase error. The control pulses are sent to the Loop Filter (LF) to generate a control voltage responsible to adjusting the frequency and phase of the VCO output.

At the receiver side, the CDR samples the actual data signal at sampling instance ts and compares the sampled value with a threshold voltage Vt. If the value is bigger than Vt, logic “1” is received; otherwise, logic “0” is received. An ideal receiver samples data in the middle of each data bit. Without amplitude noise, the receiver can always correctly recover the transmitted bit. Under the presence of jitter and noise, the transition edge of the signal can fluctuate horizontally across the sampling point (along the time axis), and the signal voltage can fluctuate vertically at the sampling point (along the voltage axis).

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